The theorem and conditions on identifying undetectable faults can be acquired by applying combinational ATPG to ILA in sequential circuits; and the conditions are given for faulty circuit.
對(duì)時(shí)序電路的迭代邏輯陣列(ILA)施加組合ATPG(自動(dòng)測(cè)試模式生成),可得到不可測(cè)故障識(shí)別的定理和條件,其條件針對(duì)故障電路給出。
This paper introduces fault model and design flow of the ATPG (automatic test pattern generation) techniques, which are utilized to test RSIC CPU manufacturing defects along with DFT(design for test) technology.
介紹了自動(dòng)測(cè)試模式生成的測(cè)試故障模型和設(shè)計(jì)流程，以及自動(dòng)測(cè)試模式生成結(jié)合可測(cè)性設(shè)計(jì)技術(shù)在測(cè)試ＲＳＩＣ ＣＰＵ制造缺陷中的應(yīng)
The goal of Automatic Test Pattern Generation(ATPG) is to reduce generation time and improve quality of test pattern, and the two key steps of ATPG are generation and optimization of test pattern set.
本文以航天科工集團(tuán)公司課題:“面向數(shù)字測(cè)試的自動(dòng)測(cè)試模式生成開(kāi)發(fā)環(huán)境”為背景,針對(duì)數(shù)字電路測(cè)試和故障診斷中的測(cè)試生成問(wèn)題,以基本蟻群算法為基礎(chǔ),研究數(shù)字電路測(cè)試模式的生成和優(yōu)化技術(shù)。